Stanford HPC Seminar Series: Introduction to Intel Trace Analyzer and Collector

Interested in better understanding the behavior of your MPI application? Want to quickly find bottlenecks, and achieve high performance for your parallel applications? Intel is coming to Stanford to host this seminar on Intel Trace Analyzer and Collector.
What:
Introduction to Intel Trace Analyzer and Collector,
Introduction to Intel MPI/OpenMP
Presented by Gergana Slavova, Intel
When:
August 20th, 1:30pm – 3:30pm
(pizza served starting at 1:00pm)
Where:
ME Design Building
416 Escondido Mall
Room 200 Teaching Studio
Agenda:
1. Intel MPI Library
 a. overview
 b. OpenMP/MPI hybrid support
2. Intel Trace Analyzer and Collector
 a. Tracing your MPI application with Intel Trace Collector
 b. Performance Analysis with Intel Trace Analyzer
 c. Demo (Poisson + application from Stanford)
 d. Ideal Interconnect Simulator & Imbalance Diagrams
 e. MPI Performance Snapshot
 f. MPI Correctness checking
Additional detail on location:
Building 550 (see map), also known as Peterson Laboratory. The street address is 416 Escondido Mall, but the building entrance closest to the Design Group offices is on Panama Mall, across from the Mechanical Engineering Research Lab (MERL).