Stanford HPC Summer Speaker Series: Guided Code Vectorization with Intel® Advisor XE – July 19@noon

Date for Tutorial: Tuesday, 19 July, 2016
Time: Noon
Duration: 1.5 hours
Location: d.school (Peterson Engineering Laboratory, 550 Panama Mall, Room 200)
 
Title: Guided Code Vectorization with Intel® Advisor XE
 
Abstract:
In this topic we discuss the usage of an optimization tool called Intel® Advisor. The discussion is illustrated with an example workload that computes the electric potential in a set of points in 3-D space produced by a group of charged particles. The example workload runs on a many-core Intel Xeon Phi processor (formerly Knights Landing) with Intel AVX512 instructions.

The application was originally parallelized across cores, but otherwise neither optimized nor vectorized. In the publication, we discuss three performance issues that the Intel Advisor detected: vector dependence, type conversion and inefficient memory access pattern. For each issue, we discuss how to interpret the data presented by the Intel Advisor, and also how to optimize the application to resolve these issues. After the optimization, we observed a 27x performance boost compared to the original, non-optimized implementation.

Speaker Bio:
Ryo Asai
 is a Researcher at Colfax International. He develops optimization methods for scientific applications targeting emerging parallel computing platforms, computing accelerators and interconnect technologies. Ryo holds a B.A. degree in Physics from University of California, Berkeley.